The Rambus XDR™ memory architecture is a total memory system solution that achieves an order of magnitude higher performance than today's standard memories while utilizing the fewest ICs. Perfect for compute and consumer electronics applications, a single, 4-byte-wide, 6.4Gbps XDR DRAM component provides 25.6GB/s of peak memory bandwidth.
Key components enabling the breakthrough performance of the XDR memory architecture are:
XDR DRAM is a high-speed memory IC that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 7.2Gbps data rates providing up to 28.8GB/s of bandwidth with a single device.
XIO controller IO cell provides the same high-speed signaling capability found on the DRAM, but adds additional enhancements like FLEX PHASE technology that eliminates the need for trace length matching.
XMC memory controller is a fully synthesizable logical memory controller that is optimized to take advantage of innovations like DYNAMIC POINT-TO-POINT which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
XCG clock generator provides the system clocks with four programmable outputs and is guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices
Key components enabling the breakthrough performance of the XDR memory architecture are:
XDR DRAM is a high-speed memory IC that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 7.2Gbps data rates providing up to 28.8GB/s of bandwidth with a single device.
XIO controller IO cell provides the same high-speed signaling capability found on the DRAM, but adds additional enhancements like FLEX PHASE technology that eliminates the need for trace length matching.
XMC memory controller is a fully synthesizable logical memory controller that is optimized to take advantage of innovations like DYNAMIC POINT-TO-POINT which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
XCG clock generator provides the system clocks with four programmable outputs and is guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices
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