The P6 micro-architecture is the sixth generation of Intel x86 processor architecture, first implemented in the design of the Pentium Pro CPU, introduced in 1995 as successor to the original Pentium P5 design.
Pentium Pro several unique architectural elements that had never seen in a PC processor and was the first mainstream CPU to a radical change in how the instructions are performed by transforming them into RISC-like micro-instructions and implement them in a very sophisticated inner core. Also has a dramatically higher performance secondary cache over all previous processors. Instead of motherboard-based cache running at a speed of the memory bus, he uses an integrated Level 2 cache with a bus that runs at full processor speed, usually three times the rate that the cache is on the Pentium.
Some of the other methods first used in the x86 space in P6 core include:
Superpipelining, the Pentium Pro with a 14-stage pipeline, compared to Pentium's 5-stage
Wider 36-bit physical address bus for more than 4 GB of physical memory
Speculative execution and out-of-order, so new retirement units in the execution core that fewer pipeline stalls and contributed to the Pentium Pro increased speed scaling
Register renaming, creating a more efficient execution of multiple instructions in the pipeline.
Intel's first new chip since the Pentium Pro lasted almost a year and half to produce, and when it finally seemed the Pentium II proved to be very one evolutionary step in the Pentium Pro. This led to speculation that one of Intel's main objective when creating the Pentium II was away from the expensive integrated Level 2 cache, which was so hard to produce the Pentium Pro. Architectural, the Pentium II is not very different from the Pentium Pro, with a similar x86 emulation core and most of the same functions.
Pentium II improved on the Pentium Pro architecture by doubling the size of level 1 cache to 32KB with special caches to improve the efficiency of processing 16-bit code (the Pentium Pro is optimized for 32-bit processors and does not include 16-bit code as well) and increase in write buffers. But the most controversial aspect of the new Pentium II was the packaging. The integrated Pentium Pro secondary cache, running at full processor speed, was replaced on the Pentium II with a small circuit with the processor and 512KB of secondary cache, running at half the speed of processor. This meeting, as a single-edge cartridge (SEC), is designed to fit on a 242-pin slot (8 Socket) on the new style Pentium II motherboard.
Intel Pentium III - was launched in the spring of 1999 - does not give rise to architectural improvements after the addition of 70 new Streaming SIMD Extensions. These rival AMD offered the opportunity to take the lead in processor technology race, which they seized a few months later with the launch of the Athlon processor - the first seventh-generation processor.
The P6 architecture lasted three generations of the Pentium Pro to Pentium III, which is characterized by a low power, integer performance and a relatively high instructions per cycle (IPC).
Pentium P5 Microarchitecture
Posted by Gopi Krishnan / Comments: (0)
First once introduced in 1993, Pentium was the successor to the Intel 486 line of CPU's, and the processor in the fifth generation.
The original Pentium microprocessor, the internal code name P5 and a pipeline to be superscalar microprocessor, produced using a 0.8 micron process. It was followed by P54, a shrink of the P5 a 0.6 micron process that was double processor ready and has an internal clock speed different from the front side bus (it is much more difficult for the bus speed than the internal clock). In contrast, P54 was followed by the P54C, which used a 0.35μm process - a pure CMOS process, unlike Bipolar CMOS process that was used for older Pentium.
The main architectural changes that stated Pentium's increased performance over the 486 chips that preceded his:
Superscalar architecture: Pentium has two data paths (pipelines), making it possible for more than one instruction per clock cycle. A pipe (the "U") a circular, while the other (the "V") may be the simplest, most common instructions. Using more than one pipeline is a typical example of RISC processor design, and marked the beginning of what would Intel increased use of RISC technology in the Pentium family of processors.
64-bit data path: The doubling of the data bus width means that twice the amount of information previously chips could manage was read in each memory retrieval.
The subsequent P55C Pentium MMX processor is based on the P5 core and used the 0.35μm process. It offered more significant improvements by doubling the size of the built primary cache to 32KB and by extending the instruction to optimize the treatment of multimedia functions.
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