ALLCOMPUTERNEWS: Palomino

The first concerns the Processor's Transition Lookaside Buffer (TLB). The TLB is best thought of as just another cache which - like the better known L1 and L2 caches - provides a mechanism that further enables the CPU to avoid inefficient access to main memory. Specifically, the TLB caches hold data used in the translation of virtual addresses into physical addresses and vice versa. The probability of a CPU finding the address it needs in its TLB - known as the processor's TLB hit-rate - is generally very high. This is just as well, because conversely, the penalty when a CPU fails to do so can be as much as three clock cycles to resolve a single address.

The Thunderbird core had only a 24-entry L1 TLB instruction cache and a 32-entry L1 TLB data cache. This compares unfavourably with the Pentium III, which has a 32/72-entry L1 TLB. The Palomino goes some way towards redressing the balance, providing a 24/40-entry L1 TLB in addition to a 256/256-entry L2 TLB - unchanged from its predecessor. A further improvement is that - like its L1 and L2 caches - the Palomino's L1 and L2 TLB caches are guaranteed not to contain duplicate entries.

Whilst the new core's L1 and L2 cache sizes and mappings remain unchanged, what is different is the Palomino's automatic data prefetch mechanism that works alongside its cache. This predicts what data the CPU is likely to need and fetches it from main memory into its cache in anticipation of its request. An evolution of previous designs that have been around for some time, the Palomino's includes a feature which allows software initiated data prefetch functions to take precedence over the core's own mechanism.

Hitherto, the Athlon processor has supported only a partial implementation of Intel's SSE technology. The third major improvement over its predecessor sees the Palomino add a further 52 new SIMD instructions to those supported previously. AMD had dubbed the original 21 SIMD instructions implemented "3DNow!" and the 19 added subsequently "Enhanced 3DNow!". With Palomino's implementation of the full SSE instruction set AMD's associated terminology has been revised to subsequently "3DNow! Professional".

A further innovation is the Palomino's OPGA (organic PGA) packaging, which replaces the somewhat dated CPGA (ceramic PGA) arrangement used by earlier cores. As well as being lighter and cheaper to produce, the new organic material - which is similar to that used on recent Intel CPUs, albeit brown in colour rather than green - confers advantages in thermal behaviour and greater elasticity than the ceramic material used previously. By allowing capacitors to be mounted closer to the core of the CPU on the underside of the packaging, both delivery of power to the core and the ability to filter out noise are improved.

Despite being very different from the previous CPGA packaging, OPGA continues to be based on the well-established 462-pin Socket A form factor, meaning that new Palomino-based CPUs should fit existing Socket A motherboards. For them to work, however, will require both a BIOS upgrade to ensure the new processor is properly recognised and - since the new processors are designed to support operation at 133MHz only - for the motherboard to allow the FSB to be clocked at this frequency.

In move that harked back to the ill-fated "P-rating" system first introduced by rival chipmaker Cyrix in the mid-1990s, AMD's XP family of processors is not referenced according to clock speed, but rather are assigned "Model Numbers". AMD's rationale for doing this is well understood.

The XP family originally comprised four models - 1500+, 1600+, 1700+ and 1800+ - operating at clock speeds of 1.33GHz, 1.40GHz, 1.47GHz and 1.53GHz respectively. By the beginning of 2002 the range had been extended to the XP 2000+. In deference to AMD's model numbering strategy, suffice to say that this is likely to have equivalent performance to a 2GHz Pentium 4 processor!