XDR memory interfaces use Octal Data Rate (ODR), transferring 8 bits of data per clock cycle. ODR enables 3.2 GHz data rates with a 400 MHz clock and provides a scalable path to over 8.0 GHz as bandwidth needs increase.
The lower speed 400 MHz system clock is routed on the PCB to the memory controller and DRAM devices. On-chip, the 400 MHz clock is multiplied up to 1.6 GHz with a PLL. This effective 1.6 GHz clock is subsequently used to transmit and receive data on both clock edges, resulting in 3.2 GHz data rates. The 1:8 relationship between clock and data rates results in Octal Data Rate (ODR) operation.
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